Abstract/Details

Process design for yield in deep submicron devices


2008 2008

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Abstract (summary)

Interaction between the manufacturing process and the circuit has become a major source of the yield loss in nanometer nodes of the current day semiconductor manufacturing. In this thesis author attempts to formalize a framework for both designers and process engineers to solve process and design interaction related yield problems. The "process design" for yield framework offers a systematic methodology for understanding these interactions and provides solutions while considering the implementation cost and manufacturability. The framework discussed in this thesis consists of three major stages. The first step is identifying the nature of the fails. In the second step, a relationship between chip parameters to the building block of the circuit—transistors, resistors, capacitors etc is established. The third step involves relating the devices to individual process modules and process steps. The novelty of current proposal is an increase in yield without either radically changing the process or re-doing the design, both of which are expensive. The experimental evidence towards applicability of the framework is provided through case study approach. The three case studies presented in here were taken from a high volume deep submicron semiconductor manufacturing environment. In the case study 1 and case study 2, yield loss mechanisms due to chip level parameters were studied. Through systematic analysis of the fail signature, a relationship between device parameters and the chip parameters was established. The device parameters were then related to process parameters. Solutions to yield problems were obtained by performing the cost vs. benefit analysis. In case study 3, functional fail mechanism was addressed. Using root mean square (RMS) methodology, a relationship between the process module and the functional fails was established. Individual process controls were evaluated and optimized by balancing cost of implementation with yield gain. The applicability of proposed framework is successfully proven in silicon. Author expects that "process design" for yield framework would bridge the knowledge gap that exists between the FAB-less design community and the integrated (semiconductor) device manufacturers (IDM).

Indexing (details)


Subject
Electrical engineering
Classification
0544: Electrical engineering
Identifier / keyword
Applied sciences; Circuit design; Deep submicron devices; Semiconductor manufacturing; Yield loss
Title
Process design for yield in deep submicron devices
Author
Desu, Chandra S.
Number of pages
137
Publication year
2008
Degree date
2008
School code
0118
Source
DAI-B 69/08, Dissertation Abstracts International
Place of publication
Ann Arbor
Country of publication
United States
ISBN
9780549663737
Advisor
Desu, Seshu B.
Committee member
Anderson, Neal; Rastogi, Alok C.; Watkins, Jim
University/institution
University of Massachusetts Amherst
Department
Electrical & Computer Engineering
University location
United States -- Massachusetts
Degree
Ph.D.
Source type
Dissertations & Theses
Language
English
Document type
Dissertation/Thesis
Dissertation/thesis number
3315495
ProQuest document ID
230667695
Copyright
Database copyright ProQuest LLC; ProQuest does not claim copyright in the individual underlying works.
Document URL
http://search.proquest.com/docview/230667695
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