Improving functional density through run-time circuit reconfiguration
The dense array of programmable logic and rich interconnect of modern FPGAs make them ideal for solving many application-specific computing challenges. By specializing all aspects of a computing structure, these FPGA based architectures achieve unusual levels of efficiency and performance. The benefits of gate-level specialization can be extended by reconfiguring an application-specific computing structure at run-time. This technique, termed run-time reconfiguration (RTR), allows dynamic conditions to dictate the optimal computing architecture within the programmable logic resources.
The use of this technique, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against this reconfiguration cost. This metric is used to justify RTR within a special-purpose computing architecture and identify the effects of reconfiguration time within a run-time reconfigured application. Several run-time reconfigured applications are presented and shown to provide greater functional density than a conventional, statically configured alternative.
Since the functional density of such run-time reconfigured systems is so sensitive to reconfiguration time, configuration improvement methods have been suggested. Several configuration improvement techniques are reviewed and analyzed using the functional density metric. Techniques that reduce device configuration time increase the functional density of RTR applications and extend the benefits of RTR to additional configurable computing applications.
0984: Computer science