Digital compensation of dynamic acquisition errors at the front-end of ADCs
In Analog-to-Digital Converter (ADC) applications such as wireless base stations, sub-sampling at an Intermediate Frequency (IF) is an attractive method for minimizing component count and system cost. By applying this method, one or more steps of down-conversion are removed from the receiver path and some of the analog front-end signal processing functions can be moved to the digital domain. In such a solution, the ADC's linearity at high input frequencies becomes a critical issue. Despite the use of a dedicated track-and-hold amplifier (THA), nonlinearities in the circuit's input network often introduce dynamic errors that limit the performance of the ADC at high input frequencies.
A number of analog techniques have been proposed in the past to improve the linearity performance of the ADC's front-end. However, most of these techniques suffer from bandwidth limitations in the active analog circuitry and lose their performance at high input frequencies. In recent years, the continuous scaling of CMOS technology has resulted in low cost and high performance digital circuits. This has provided the feasibility to integrate complicated digital signal processing on chip and therefore use digital correction methods to compensate circuit nonlinearities in ADCs. However, these techniques mainly address static errors in the converter core and are not effective at removing dynamic nonlinearities at the front-end of the ADC.
This dissertation introduces a digital enhancement scheme that is specifically tailored to remove high frequency distortion caused by the dynamic nonlinearities at the sampling front-end of ADCs. The basic concept of digital compensation here is to apply the inverse nonlinear function to the digital output of the ADC in order to minimize its error over the desired frequency range. Conceptually, a nonlinear system with memory can be modeled with a Volterra series. However, the inverse Volterra series becomes very complex as the order of nonlinearity and memory in the system increases and it requires intensive computational power that is impractical even in today's fine-line technology. Our proposed algorithm uses information about the sources of nonlinearity and judicious modeling to simplify the digital post processing scheme.
The main sources of dynamic error at the front-end of ADCs are investigated and analyzed in order to find a compact model for frequency-dependent nonlinearities in this stage. This model is then used to build a nonlinear filter in the digital domain for compensating the nonlinearities. The coefficients of the filter are calibrated using training signals in the desired frequency region. The correction scheme can be effectively used for canceling nonlinearities across the whole input bandwidth of the ADC.
Measurement results from applying the proposed method to a 14-bit commercially available ADC are presented at different frequency ranges. The experimental results show an improvement in SFDR of the ADC to more than 83 dB up to input frequencies of 470 MHz. Measurement results show that the algorithm is not very sensitive to temperature variations and is also applicable to any sub-sampling ADC that suffers from linearity degradation at high input frequencies.