Abstract/Details

Fractional-N synthesizer architectures with digital phase detection


2008 2008

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Abstract (summary)

During the last decade there has been unprecedented growth in the use of portable wireless communications devices for applications as diverse as medical implants, industrial inventory control, and consumer electronics. If these communication devices are to be low power, flexible, and reconfigurable, new radio architectures are needed which take advantage of the major strength of state-of-the-art digital manufacturing processes; that is the ability to build large, complex low power signal processing circuits, with extremely fast clocking speeds. However, traditional radio architectures rely on analog techniques which are ill suited for the use in modern highly integrated digital systems.

A critical component of a radio system is the frequency synthesizer, a circuit which can accurately synthesize and modulate high frequency signals. Traditional synthesizers still utilize a significant amount of analog circuitry. In this work, techniques are developed to replace this analog circuitry with digital equivalents. To do this, a digital phase detection scheme for a Fractional-N Phase Lock Loop (FPLL) is presented. The all-digital phase detector can be used as an alternative to a conventional analog-intensive phase detector, charge pump and loop filter blocks.

Another limitation of traditional synthesizers is the difficulty in modulating the frequency of the output signal at speeds larger the FPLL's bandwidth. A new technique is developed for modulating the output frequency of the FPLL at rates significantly faster than the loop bandwidth would typically allow. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated. The new scheme does not compromise on the frequency accuracy of the output signal. The key ideas presented have been proven in a proof of concept design. A prototype 2.2GHz fractional-N synthesizer, incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142kHz, an FSK modulation rate of 927.5kbs is achieved. The prototype is implemented in 0.13μm CMOS and consumes 14mW from a 1.4V supply.

Indexing (details)


Subject
Electrical engineering
Classification
0544: Electrical engineering
Identifier / keyword
Applied sciences; Digital phase detection; Frequency synthesizers; Phase locked loops
Title
Fractional-N synthesizer architectures with digital phase detection
Author
Ferriss, Mark A.
Number of pages
114
Publication year
2008
Degree date
2008
School code
0127
Source
DAI-B 71/02, Dissertation Abstracts International
Place of publication
Ann Arbor
Country of publication
United States
ISBN
9781109594959
Advisor
Flynn, Michael
University/institution
University of Michigan
University location
United States -- Michigan
Degree
Ph.D.
Source type
Dissertations & Theses
Language
English
Document type
Dissertation/Thesis
Dissertation/thesis number
3392771
ProQuest document ID
304575223
Copyright
Database copyright ProQuest LLC; ProQuest does not claim copyright in the individual underlying works.
Document URL
http://search.proquest.com/docview/304575223
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