Performance -driven synthesis of sequential circuits
This proposal describes a comprehensive methodology for performance-oriented synthesis of multi-level sequential logic circuits. The proposed methodology covers the two dominant design flows (i) synthesis from behavioral descriptions of FSMs, and (ii) iterative improvement of gate-level netlists.
Despite the numerous advances in the field of synthesis and optimization of digital circuits and the wealth of literature on the subject, synthesis of synchronous sequential circuits remains an open problem . Much of the previous work in sequential logic synthesis have targeted minimization of the implementation area. Performance is usually considered in the later phases of synthesis using techniques such as performance driven re-synthesis of the combinational logic component and gate-level retiming of the latches. While this results in some exploration of the design space, the state encoding is largely fixed and the logic optimization attempts to improve the logic implementation under the given state assignment. As a result of this inadequate exploration of the design space, design quality suffers and designs frequently fail to meet the performance goals. This leads to increased design iterations, reduced designer productivity and poor design quality. This problem is further aggravated by the increasing design complexity, greater time-to-market pressures and ambitious performance goals of present day designs.
To alleviate these problems we present enhancements to the current design methodologies. We present a novel unified mathematical and algorithmic framework that facilitates the study of state encoding, retiming and re-encoding of behavioral and gate-level representations. Within this common framework, we consider the following problems. In the area of synthesis from behavioral descriptions, we propose (i) performance-oriented FSM partitioning, and (ii) state encoding. In the area of iterative refinement of gate netlists, we present techniques for ( i) latch removal and re-encoding of circuits compiled from hardware description languages, and (ii) retiming and resynthesis techniques that maintain the initial number of registers.
We show that the circuits designed by the proposed methodologies have superior performance compared to those generated by conventional performance driven synthesis techniques. Moreover, the area overheads of the proposed techniques is much smaller than the previous approaches. The proposed techniques fits into the conventional synthesis flows. The effectiveness of the proposed methodology stems from (i) consistent consideration of performance at all stages of the design, and (ii) identification of useful behavioral and structural transformations that lead to a better exploration of the design space. We believe that the proposed design methodology would allow the designer to meet the timing goals of the design with fewer design iterations.