Logical hardware debuggers for FPGA -based systems
Designers using Field Programmable Gate Arrays (FPGAs) have generally performed hardware debugging and verification for FPGA designs much like they would for other digital hardware designs, using simulation and external test equipment. Due to common SRAM-based FPGA device features such as JTAG interfaces, configuration readback, and reprogrammability, the debugging process for FPGA designs can resemble common software debugging approaches where designs are debugged by executing directly on the target hardware system using debuggers which provide high levels of design observability, controllability, execution control, and interactivity while presenting high-level, logical views of the designs. This dissertation demonstrates that such a hardware debugging system is possible for FPGA-based designs by developing such a system for FPGA-based custom computing machines (FCCMs) using the JHDL design environment and other tools such as JBits and JRoute. This dissertation also demonstrates the use of FPGA configuration readback for providing FPGA design observability support for hardware debuggers as well as the use of design modification or instrumentation to improve design observability, controllability, and execution control. The most notable of these design instrumentation or modification techniques are: design-level scan, which provides complete design observability and controllability; bitstream-modifiable embedded logic analyzers, which provide quickly configurable, localized observability; and bitstream modification for the interactive controllability of an FPGA design's state.
0984: Computer science