Temperature aware techniques for design, simulation and measurement in microprocessors
Temperature aware chip designs have gained importance and popularity in recent years. In this dissertation, we present several temperature aware techniques to reduce the temperature of the chip, to speedup thermal simulations, and to provide live thermal measurements in microprocessors. They include: (1) Temperature aware floorplanning: reducing the maximum temperature of the CPU chip through floorplanning. Through careful block placement, temperature aware floorplanning is able to greatly improve the temperature distribution of the chip while maintaining comparable performance. Experimental results show that it is possible to find a floorplan that can reduce the maximum temperature of a chip by up to 21°C compared to the original floorplan while keeping the total wire length of the chip almost the same as before. (2) Fast architecture-level thermal simulation: utilizing some specific properties of the input power trace to accelerate architecture-level transient thermal simulations. Based on a linear thermal system formulation, the new method replaces many time-consuming integration computations with more efficient matrix multiplications. Experimental results show that the new method provides a speedup of up to 1000x without any accuracy loss compared to the HotSpot simulator. (3) Lightweight runtime temperature monitoring: using internal performance counters to provide detailed temperature distribution information for a CPU chip with negligible overhead. After calibration against a temperature sensor inside the CPU chip, the average temperature deviation is less than 2°C for the SPEC2000 benchmarks, showing that our tool is able to estimate the temperature distribution of a CPU chip with acceptable accuracy.