Back -gated MOSFET for power -adaptive applications
This thesis reports experimental realization of back-gated MOSFETs that can be integrated in today's technology and explains in detail why they are superior to conventional MOSFETs and how they can be utilized in power-adaptive systems. Most of the previous efforts for back-gated MOSFET fabrication have had drawbacks that prevent optimum use of back-gated MOSFET or were incompatible with existing MOS integration technology. Here, the use of previously processed field-oxide recess as a polish-stop provides the unique advantage of fabricating extremely thin single-crystal silicon layers with a uniform thickness together with back-gates with a buried interconnect network.
Experimental results for back-gated MOSFETs and conventional SOI MOSFETs are compared at 250-nm gate-length. Using Poisson's equation, an analytic discussion is provided to illustrate superior scalability of back-gated MOSFET compared to conventional SOI MOSFET due to its lower drain-induced barrier-lowering and reduced degradation of sub-threshold swing at high drain biases. The measured capacitances are used to understand the back-gated MOSFET as a capacitance network and to explore the mobility of inversion layer at back and front interfaces.
The fabrication technique does not provide self-alignment between two gates. When the back-gate is oversized to assure the overlapping of the entire back channel even with the worst-case of misalignment, the static transistor transport characteristics remain uniform. This facilitates the use of large back-gates to solving the issue of non-uniform transistor characteristics across the wafer.
One additional advantage of the double-gate structure is its operation as a non-volatile memory (NVM) with its superior scalability compared to conventional front-floating gate. Experimental write, erase and read characteristics are reported.
Finally, power-adaptive operation is demonstrated through theoretical and experimental results. Ring-oscillator simulations illustrate the power-adaptive operation using back-gate potentials while showing superior performance to conventional bulk MOSFETs. Experimental results of NMOS inverters show that lower back-gate potentials provide lower power consumption for both dynamic and static operation. In addition, a novel circuit example is provided with the circuits for multiple-valued data transmission across long interconnects. Power consumption and performance advantage is explored with consequences in noise-margin.