Abstract/Details

Performance evaluation of network-on-chip interconnect architectures


2009 2009

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Abstract (summary)

With a communication design style, Network-on-Chips (NoCs) have been proposed as a new Multi-Processor System-on-Chip paradigm. Simulation and functional validation are essential to assess the correctness and performance of the NoC design. In this thesis, a cycle-accurate NoC simulation system in Verilog HDL is developed to evaluate the performance of various NoC architectures. First, a library of NoC components is developed based on an existing design. Each NoC architecture to be evaluated is constructed from the library according to the topology description which specifies the network topology, network size, and routing algorithm. The network performance of four NoC architectures under uniform and three non-uniform traffic patterns is tested on ModelSim 6.4. The developed NoC simulation system provides useful resources for the future development of the FPGA-based NoC emulation system.

Indexing (details)


Subject
Electrical engineering
Classification
0544: Electrical engineering
Identifier / keyword
Applied sciences
Title
Performance evaluation of network-on-chip interconnect architectures
Author
Zhou, Xinan
Number of pages
50
Publication year
2009
Degree date
2009
School code
0506
Source
MAI 48/02M, Masters Abstracts International
Place of publication
Ann Arbor
Country of publication
United States
ISBN
9781109422245
Advisor
Yang, Mei
Committee member
Das, Biswajit; Jiang, Yingtao; Kim, Yoohwan
University/institution
University of Nevada, Las Vegas
Department
Electrical Engineering
University location
United States -- Nevada
Degree
M.S.E.E.
Source type
Dissertations & Theses
Language
English
Document type
Dissertation/Thesis
Dissertation/thesis number
1469805
ProQuest document ID
305084551
Copyright
Database copyright ProQuest LLC; ProQuest does not claim copyright in the individual underlying works.
Document URL
http://search.proquest.com/docview/305084551
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