Design -for -testability for test data compression

Because the semiconductor manufacturing process introduces defects in chips, Automated Test Equipment (ATE) is necessary to identify defective chips. Testing is done by applying stimulus data to the chip inputs and evaluating the response data. The large amount of test data makes testing expensive. If the amount of test data continues to increase, test costs may even exceed the manufacturing costs for certain products. A promising solution is to store and transmit compressed stimulus data from the ATE to the chip. Additional circuitry on the chip decompresses the stimulus data and compresses the response data. The four important aspects of compression are presented: (1) stimulus compression, (2) response compression, (3) power dissipation, and (4) test quality. Test stimulus data consists of bits that are used to explicitly target faults ( care bits) and bits that can be chosen arbitrarily (don't-care bits or ds). A new stimulus data compression technique that uses a Linear Feedback Shift Register (LFSR) for decompression on the chip is presented. By enabling the LFSR state to be re-initialized at any clock cycle (instead of only at the test pattern boundaries), each initial state can be calculated such that the LFSR generates the maximum number of care bits. Simulation experiments on industrial designs are presented. During the shifting of the decompressed stimulus patterns into the scan chain, the value in each scan flip-flop may toggle many times depending on the test pattern. The toggling flip-flop values cause internal gates in the combinational logic to toggle. This may cause power dissipation concerns. A new set of techniques is presented that reduce the number of toggling flip-flops. Simulation experiments on four industrial designs are presented. Test response data consists of known responses and unknown responses (Xs), which are unknown during logic simulation, for example, due to floating busses. The main challenge in test response compression is handling the Xs. By compressing the mask bits used to force Xs to known values during response compression, the new technique results in high compression ratios in the presence of many Xs without any test quality impact.