Circuit and signaling techniques for on -chip interconnects
As VLSI progresses into Very Deep Submicron (VDSM) realms, global interconnects play an increasingly important role in the overall performance and power consumption of high-performance chips. This thesis proposes circuit and signaling solutions to the on-chip interconnect design problem. Current-sensing and phase coded signaling are proposed as potential techniques to transmit logic in current and time respectively. A test-chip verifying these techniques has been fabricated in a TSMC 0.18μ technology through MOSIS.
Using a novel receiver circuit for differential current-sensing, a performance benefit of 20% was obtained over the delay-optimal repeater insertion technique. The proposed single ended current-sensing provides more delay benefits (45% on average) and like repeaters uses one wire to transmit a data bit. The static power dissipation in current-sensing is mitigated by using transition encoded current-sensing and current-pulse signaling. These techniques are faster and lower power than repeater insertion. A hybrid circuit technique that exploits the advantages of both current-sensing and repeater insertion is proposed.
Phase coding is presented as a multi-bit signaling technique which encodes multiple bits on a single wire in terms of phase information. Transmitting multiple bits saves power and increases bandwidth. DLL based closed loop encoding and decoding schemes provide process-variation immune operation.