Synchro -tokens: A deterministic globally asynchronous locally synchronous architecture
As advances in VLSI technology enable higher levels of integration in system-on-a-chip (SoC) designs, fully synchronous implementations are becoming less feasible. Globally asynchronous locally synchronous (GALS) clocking is a promising alternative. Each core in a GALS system is a synchronous block (SB) of logic whose locally generated clock has an independent frequency and phase, while communication between cores is asynchronous. However, the nondeterministic behavior of most GALS methodologies is problematic for silicon debug and functional test. Deterministic GALS methodologies make assumptions about the profile of the asynchronous data which are valid only in a very limited set of applications.
This dissertation proposes a novel deterministic GALS methodology called “synchro-tokens” which adds parameterized wrapper logic to the interfaces of the SBs. The wrapper ensures that each transition on each asynchronous input is sensed by the SB during a deterministic cycle of the local clock. Token rings are used for handshaking and self-timed first-in first-out (FIFO) buffers for pipelined interconnect. Counters in each SB keep track of the number of local clock cycles between arrivals and departures of the token to ignore early tokens and to stop the local clock to wait for late tokens. Because no synchronizers are used, there is zero probability of metastability. The wrapper parameters, such as FIFO sizes, counter values, and clock frequencies, offer a great deal of flexibility for tuning the system performance, making the synchro-tokens methodology useful for a wide range of applications. While data flow assumptions may be made for the purpose of setting these parameters, deterministic behavior is maintained regardless of the actual profile of the asynchronous data.
The synchro-tokens architecture supports debug and test methodologies commonly applied to fully synchronous chips. The boundary scan Standard 1149.1 can be implemented with a SB whose clock is supplied through a TCK pin. Any number of internal scan chains for ATPG, BIST, or P1500 core test can cross SB boundaries by virtue of a self-timed shifting design. By interrupting the flow of tokens, system clocks can be deterministically stopped at natural breakpoints and single-stepped for cycle-by-cycle debug.