Design and analysis of charge -transfer amplifiers for low -power analog -to -digital converter applications

2004 2004

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Abstract (summary)

The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion.

First, an analysis methodology is proposed which leads to a deterministic model of the voltage transfer function. The model is generalized to any timing scheme and can be extended to account for nonlinear threshold modulation. The model is compared with simulation results and test chip measurements, and shows good agreement over a broad range of circuit parameters.

Three new charge-transfer amplifier architectures are proposed to address the limitations of existing designs: first, a truly differential CTA which improves upon the pseudo-differential configuration; second, a CTA which achieves more than 10x reduction in input capacitance with a moderate reduction in common mode range; third, a CTA which combines elements of the first two but also operates without a precharge voltage and achieves nearly rail to rail input range. Results from test chips fabricated in 0.6 μm CMOS are described.

Power dissipation in CTAs is considered and an idealized power consumption model is compared with measured test chip results. Four figures of merit (FOMs) are also proposed, incorporating power dissipation, active area, input charging energy and accuracy. The FOMs are used to compare the relative benefits and costs of particular charge-transfer amplifiers with respect to flash A/D converter applications.

The first 10-bit CTA-based A/D converter is reported. It consumes low dynamic power of 600 μW/MSPS from a 2.1 V supply, 40% less than the current state of the art of 1 mW/MSPS. This subranging type converter incorporates capacitive interpolation to achieve a nearly ideal comparator count and power consumption. A distributed sample-and-hold (S/H) eliminates the need for a separate S/H amplifier. A test chip, fabricated in 0.6 μm 2P/3M CMOS, occupies 2.7 mm2 and exhibits 8.2 effective bits at 2 MSPS.

Indexing (details)

Electrical engineering
0544: Electrical engineering
Identifier / keyword
Applied sciences; Amplifiers; Analog-to-digital converter; Charge transfer; Low-power
Design and analysis of charge -transfer amplifiers for low -power analog -to -digital converter applications
Marble, William J.
Number of pages
Publication year
Degree date
School code
DAI-B 65/03, Dissertation Abstracts International
Place of publication
Ann Arbor
Country of publication
United States
Petrie, Craig
Brigham Young University
University location
United States -- Utah
Source type
Dissertations & Theses
Document type
Dissertation/thesis number
ProQuest document ID
Database copyright ProQuest LLC; ProQuest does not claim copyright in the individual underlying works.
Document URL
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