Design validation of behavioral descriptions for arbitrary fault models
The widespread use of hardware/software systems in cost-critical and life-critical applications motivates the need for a system approach to verify functionality. Several obstacles to the verification of hardware/software systems make this a challenging problem. One issue is the high complexity of current systems which derives from both the size and the heterogeneous nature of the designs. The complexity of hardware verification has increased to the point that it dominates the cost of design. Since traditional formal verification techniques are still limited to relatively small portions of a design, researchers have explored simulation-based functional validation to verify functionality by simulating (or emulating) a system description with a given test input sequence. The tractability of validation makes it the only practical solution for many real designs today and in a foreseeable future. The largest component of validation cost is the test generation process required to ensure the detection of design errors. The cost of the test generation process derives from the largely manual nature of the process, making automation of the test generation process essential to greatly reduce design cost and time to market. In order to perform automatic test generation to detect design errors in a behavioral hardware description, this dissertation presents our research on the architecture, application, and analysis of an automatic test generation (ATG) process.
In the architecture of ATG, we propose a flexible test generation framework for the design validation of behavioral hardware descriptions in complex hardware/software systems. To achieve the flexibility necessary to target arbitrary fault models, the technique proposed in this dissertation employs a Constraint Logic Programming (CLP) formulation. We formulate the system under test as a CLP problem in order to handle both Boolean and arithmetic constraints. A state-of-art commercial CLP solver is used to solve the ATG constraints to produce test sequence for each fault.
Many existing ATG methods are typically limited to the detection of a single fault model. But in practice, no single fault model is considered sufficient to capture the wide range of errors made by designers. In order to ensure detection of a wide range of design error types, our test generation tool can target a range of various arbitrary fault models of systems under test. New fault models can be added by adding CLP constraints to the framework which we build.
To test the performance of our ATG process, a set of benchmarks with behavioral VHDL descriptions are chosen. We build a parser to automatically transform the format from VHDL descriptions to the input format recognized by our ATG framework. Validating these benchmarks makes a good start for our ATG framework to handle more, real examples in the future.
A significant obstacle to the widespread acceptance of available ATG techniques is the lack of faith in the correlation between fault models and real design errors. Although many validation fault models have been identified in previous research, the capability of these fault models to detect real design errors has never been evaluated. To evaluate the ability of our ATG tool to detect design errors, we have developed a method to analyze behavioral fault models with the detection rate of real defects.