Validation of behavioral hardware descriptions
Behavioral hardware descriptions are commonly used to represent the functionality of a microelectronic system for simulation and synthesis. The manual process of creating a behavioral description is prone to errors, so a significant effort must be made to verify the correctness of the behavioral descriptions. Simulation-based validation and formal verification are two techniques used to verify correctness of designs. We have investigated validation because formal verification techniques are frequently intractable for large designs. The first step toward a behavioral validation technique is the development of validation fault coverage metrics which can be used to evaluate the likelihood of design error detection with a given test sequence.
Design faults can be classified into a variety of classes. The hardest faults are those which present incorrect behavior only in rare corner cases. We developed three fault coverage metrics to target these corner case faults. First, the domain fault coverage detects faults on the domain boundaries by examining the test points near the boundaries since a small domain fault may only affect several points near the boundary. Second, the dataflow fault coverage metric systematically checks the coverage of selected dataflow paths, which can detect faults associated with the dataflow paths. Third, the mis-timed event (MTE) fault coverage metric detects faults that present erroneous behavior only given a critical timing sequence. These new metrics can be also adapted to the validation of hardware-software systems. Experimental results show great potential of these metrics to detect design errors of their specific classes.
0984: Computer science