Contemporary data path design optimization
As the core of most digital computing systems, data-path design is essential to determine the whole system performance. In the past decades many advanced methodologies and technologies have been proposed to optimize data-path designs. Nowadays new design requirements are emerging with the technology development: (1) Low power design. Power consumption becomes more critical issue than performance in modern data-path designs, especially for mobile device applications. (2) Extremely high performance design for micro processors. With the shrink of feature size and the increase of clock frequency, extremely high performance data-path components operated on multiple giga-hertz clock are required in micro processor designs. (3) High performance low cost design for ASIC. Application-specific design constraints, such as area/power budget and non-uniform signal required times, must be satisfied.
Inspired by these requirements, we propose two optimization techniques to efficiently minimize power consumption and achieve timing/area/power tradeoff for specific applications.
1. Binary addition is the most widely used fundamental operations. Various applications require different adder designs for high speed, small area or low power consumption. Since parallel prefix adders provide great flexibility to satisfy a specific application, we propose an integer linear programming method to build optimal prefix adders, which counts gate and wire capacitances in the timing and power models. Furthermore the proposed method can handle nonuniform arrival time and required time on each bit position. Therefore, a realistic minimal-power prefix adder can be found with arbitrary timing and area constraints.
2. Division is a fundamental but expensive arithmetic operation. We analyze the computation efforts from memory, arithmetic functions and iterations in division operation and propose a hybrid algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms together. The proposed algorithm boosts very-high radix division by efficiently estimating the reciprocal of divisor, and achieves outstanding performance-cost tradeoff. Optimizations of the basic PST algorithm are also developed to improve the performance further. The proposed algorithm is suitable for both ASIC and FPGA applications with high-performance division units.
These research works optimize data-path designs in different levels from algorithm to logical/physical synthesis. Unlike the previous works, both approaches proposed in the dissertation explore the design space in terms of timing, area and power consumption.