Cost reduction and test-quality control for scan-based testing of statistical timing defect
To reduce the test data volume and the testing application time with limited ATE channels, researchers have shown increasing interest in the areas of input stimulus compression and output response compaction. At the same time, the process variations, various noise sources, and subtle failure mechanisms in sub-90nm technologies result in significant statistical variations to both circuit timing and sizes of timing defects. Such statistical timing variations make test generation for detecting the timing failures substantially more difficult. In this thesis, we address the following two major issues: (1) testing for statistical timing defects; (2) output response compaction with high tolerance to unknown values while reducing the required storage data and shortening the test application time.
For the statistical-timing part, the key focus is to control the computation complexity imposed by the statistical timing models and also provide the accuracy considering all the interactive effects among all probabilistic factors. In this thesis, we first propose an efficient test-generation flow for statistical timing defects. A key component called pattern selection is introduced in this test-generation flow to reduce the size of the test set while maintaining effective detection of statistical timing defects (which is imposed by the process variation). Second, we develop a static statistical timing analyzer for latch-based pipeline designs. This timing analyzer can report the structural circuit-timing criticality considering the correlations of critical-timing events both inside the pipeline stages and across the pipeline stages.
For the test-response compaction part, the key focus is to tolerate unknown values among the test responses while achieving maximal compaction ratio. First, we introduce a DFT module, named response shaper to reshape the scan-out responses before feeding them to a space compactor. Along with the proposed reshaping algorithm, response shapers can help the space compactor to reduce the number of undetectable modeled and un-modeled faults in the presence of unknown values. Second, we propose a novel response compactor, named ChiYun compactor, to compact scan-out responses in the presence of unknown values. By adding storage elements into an Xor network, a ChiYun compactor can offer multiple chances for a scan-out response to be observed at ATE channels in several scan-shift cycles. Third, we develop a mathematical framework to analyze the unknown tolerance of a space compactor based on its modeled-fault coverage or n-detection metric. With this analysis, we further propose a design flow to construct a space compactor with maximal compaction ratio and desired level of test quality. Last, we propose a hybrid compaction scheme using a space compactor along with an unknown-blocking time compactor. This hybrid scheme can guarantee the same modeled-fault coverage as no compaction scheme is applied and also observe a desired percentage of scan-out responses.
0984: Computer science