A 10-bit 100MHz analog -to -digital converter in 0.25μm CMOS using folding, interpolation and averaging techniques
Low-latency high-speed analog-to-digital (A/D) converters are traditionally implemented in flash architectures, but the large area and high power consumption limit their applications to low resolutions. By preprocessing the input signal with a nonlinear circuit, folding architectures are able to provide both high speed and low latency in a medium resolution A/D converter while maintaining the area and power consumption at reasonable levels.
Device mismatch places a fundamental upper limit on the trade off between resolution, speed and power in A/D converters. Newer CMOS technologies demand a lower supply voltage, thus decreasing the input signal range and increasing the matching requirements. High costs prohibit the use of trimmed devices and digital correction techniques are not always feasible in high-speed low-latency architectures. Larger transistors in the input preamplifiers will improve precision but at the price of increased power consumption, die size and decreased sampling rate.
This thesis describes a 10-bit folding and interpolating A/D converter designed in a 0.25μm CMOS process utilizing an improved offset averaging technique for reducing the effect of transistor mismatches without sacrificing the gain. The averaging mechanism is thoroughly investigated and an optimization procedure is proposed. In order to further enhance the performance, the design employs a compensating capacitor technique and current steering folding amplifiers. The A/D converter achieves an ENOB of 9.7bits with a 195kHz input signal frequency and 8.8bits with a 49.8Mhz input signal at 100Msample/s while dissipating 150mW of static power from a 2.5V power supply.