An accurate and time-efficient cross-talk noise model for multi-line circuits
With increased scaling, crosstalk noise between signal wires has become a major source of failures in VLSI systems. Due to large number of coupled nets, it is now impractical to use SPICE simulation methods for VLSI chips. Therefore noise estimation alternatives have been sought. The crosstalk model proposed in this work presents a highly accurate and time-efficient method to estimate the crosstalk noise for use in physical design automation. For the first time, a complete multi-line noise model is proposed where active aggressors are modeled by current sources and passive aggressors are represented by equivalent capacitances. The general formulas derived can easily be applied to real cases. Noise peak and width expressions are derived and results are in good agreement with HSPICE results. Results show that average error for noise peak is 4.57% and for the width is 4.95% while allowing for ten times faster analysis than HSPICE.