Analog circuit design for embedded and high performance processors in nanoscale technologies
Embedded and high-end processors' performance demands have caused the semiconductor industry to scale their processes to nanometer dimensions. Unfortunately, traditional analog circuits have become increasingly difficult to implement in nanoscale processes. However, analog-to-digital converters and phase-locked loops are critical to the operation of processors in their respective markets. This work addresses the challenges encountered when these two functions are implemented in nanoscale SOI CMOS.
To combat process variation and second-order effects unique to analog-to-digital converters, a novel current mirror and a comparator offset cancellation technique are developed. Results show that the novel current source can achieve full accuracy in a 90nm technology, limited only by channel-length modulation effects, whereas a standard current mirror can only achieve a 70% accuracy. The offset cancellation technique provides nearly 20x area and 5x power improvement over traditional techniques while canceling input offsets as large as 20mV.
To facilitate 6FO4 clocking strategies, phase-locked loops utilizing novel oscillator topologies were developed in 65nm PD-SOI and 180nm bulk technologies. These topologies allow for higher frequencies than traditional implementations. Experimental results from a TSMC 180nm process show oscillation frequencies as high as 4.5GHz and RMS jitter values as low as 875fs. A stand-alone all-digital duty cycle corrector, which is critical for clock management in high-end processors, is also developed. Results show that this circuit can correct the duty cycle of a clock to within 1% of any desired value.
The sum of the work in this thesis provides a framework for the development of analog-to-digital converter and phase-locked loop circuitry for the embedded and high-end nanoscale markets.