Impact of strain on memory and lateral power MOSFETs
To circumvent the limitations of conventional scaling, the semiconductor industry incorporated strained silicon technology to boost the performance of digital logic devices. Since strain alters several semiconductor properties, its effect on all device parameters needs to be investigated. This work focuses on the effect of mechanical stress on memory and power devices.
Growth of digital electronics is largely attributed to the success of CMOS memory such as DRAM and Flash. The most significant device characteristic for memory is the duration of time for which the memory cell is capable of storing the data with integrity or ‘retention time’. Using four-point wafer bending apparatus to apply mechanical stress the dependence of memory retention time on strain is studied. From measurements it was observed that while DRAM retention degenerates with mechanical stress, NVM improved with tensile stress.
Power MOSFETs are used as high current and voltage drivers in automotive, telecommunication and power industries. The two main figures of merit of power devices are their on-resistance and breakdown voltage. The design of these devices is complicated by the tradeoff between the requirements for minimum on-resistance and maximum breakdown voltage. This work focuses on the application of mechanical stress to improve the performance of Lateral Diffusion MOSFET. The device behavior was analyzed by measuring and extracting piezoresistance coefficients of these devices and by monitoring avalanche breakdown with mechanical stress. It was found that the on-resistance reduced with stress, while breakdown voltage remained a constant thus making strain a viable performance booster in these devices.
With the understanding of device behavior with strain, the application of stress via process was simulated with FLOOPS and Sentaurus process. The amount/type of stress present in device gives insight into strained device structure and performance.