Design of integrated frequency synthesizers and clock-data recovery circuits for 60 ghz wireless communications
Over the past few decades the capabilities of portable electronic devices have been constantly improving thanks to the advances in semiconductor technologies and packaging schemes. The consequent availability of compact devices capable of efficient and fast data elaboration took advantage of the flexibility that the capillary diffusion of wireless connections has brought. But the ever increasing processing capabilities of integrated electronics has been driving the consumer expectations to the point where the required data rate has exceeded the wireless infrastructure capabilities by hitting the wall of bandwidth limitations. In this ever growing demand for bandwidth, the recent release of the 7 GHz spectral window around 60 GHz by FCC has generated tremendous expectations and motivated several organizations to elaborate standards and proposals to address the 60 GHz band use.
The design and implementation of a radio transceiver operating in the 60 GHz range is not a straightforward task. To be convenient for consumer electronics, such a device should feature low cost, low power consumption, small form factor, and operate over a spatial range sufficient to enable free movements in a living space. Such requirements rule out the costly compound semiconductors solutions (e.g. SiGe, GaAs) and mandates the integration of the base band signal processing on the same die where the high frequency conversions are performed. The obvious candidate to meet the requirements is then the CMOS technology. The benefit of the CMOS solution relies in its low cost and in the embedded compatibility with digital integration. However, the CMOS platform introduces several challenges as well. First, silicon substrates are notoriously lossy when compared to other semiconductors. The substrate losses will limit the quality factor of integrated inductors and, consequently, the performances of all the millimeter-wave integrated blocks like VCO, mixer, and LNA. Also, the maximum operating frequency of modern CMOS processes is considerably lower than bipolar counterparts. It is also well known that the noise performance of a CMOS process is worse than that of bipolar or compound semiconductors processes. More specifically, the flicker corner frequency in CMOS devices tends to be much higher than in bipolar counterparts. This last aspect introduces a performance detriment in the oscillators phase noise and, therefore, will pose serious challenges in the design of frequency synthesizers.
This dissertation presents the development of a 60 GHz-standard compatible fully integrated CMOS frequency synthesizer for 60 GHz applications, and describes the design of two clock data recovery (CDR) circuits for base band signal processing in 60 GHz transceivers. The frequency synthesizer has been implemented as a phase locked loop (PLL) and has been laid out in a bulk 90 nm CMOS process from STMicroelectronics. The presented PLL frequency synthesizer features embedded programmability: it supports the 4 standard-defined channels spanning from 49.68 to 56.16 GHz with 2.16 GHz channel spacing, dual-core cross-coupled VCO, programmable frequency divider chain, and programmable closed loop bandwidth. The two CDR architectures feature a high speed fully-differential implementation and a low-power single ended solution. Both CDRs have been implemented in the same standard 90 nm CMOS process used for the millimeter-wave PLL frequency synthesizer, and their functionality has been validated in the context of a fully integrated 60 GHz wireless transceiver operating over a wireless link of 1.5 m.