Optimizing Network-on-Chip Designs for Heterogeneous Many-Core Architectures

Abstract

On-chip Interconnection Networks are shifting from multicore to manycore systems and are tending to be heterogeneous with the integrated modules from different vendors of various sizes and shapes. Each module has different properties such as routers, link-width. From a system designer's perspective, making layouts of metal-wired links among interconnection modules for communication will be impractical as it increases the design cost in terms of the communication complexity and power leakage on these links. We can replace all links with wireless or optical links for high-performance, reducing latency. However, it comes with a high-cost. Therefore, we formulate the optimization model to minimize the cost (communication links between subnets) and maximize their data flows in the network-on-chip.

Since the optimization model using the optimizers such as CPLEX and Gurobi to achieve the best possible solutions, the solution time to a large set of given problems is not acceptable. Hence, we present a mincostflow-based heuristic algorithm (LINCA) that minimizes the quantification of hybrid routers corresponding to the application-specific traffic for manycore systems. LINCA guarantees the performance of hybrid networks on chip. Its results are validated against the manycore system architecture. Our evaluation shows that LINCA can significantly reduce the cost of using hybrid routers (communication links) in the manycore systems. It reduces cost by 84 percent on average across a variety of applications, compared with all of hybrid routers being deployed in the network without using the optimization model. However, we observed that the solution time of LINCA is increased exponentially for large scale networks. We then proposed an efficient predictive framework for optimized reconfiguring on-chip interconnection network.

The predictive model is built based on the optimization model and learning-based algorithms. As we wish to reduce the communication complexity of the interconnection links in the entire on-chip network, our objective is to minimize those links corresponding to the application-specific traffic demands. Thereby, the overall power dissipation can be mitigated. We believe that our approach will be an essential step when scaling out.